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NXP Semiconductors /QN908XC /CS /CTRL0

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Interpret as CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)ENABLE 0 (SRST)SRST 0OSC_FREQ0CLK_DIV

ENABLE=DISABLE

Description

CapSense control register 0

Fields

ENABLE

CapSense enable. Write 1 to start work, 0 to stop.

0 (DISABLE): OSC work disable.

1 (ENABLE): OSC work enable.
SRST

Soft reset. Set 1 to reset, and 0 to de-assert.
OSC_FREQ

Oscillation frequency control. The driving current will change accordingly.
CLK_DIV

Clock divider from CLK_APB : CLK_CS_DIV = CLK_APB/(CLK_DIV + 1)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data